CQRS08

         CQRS08 - Command Queuing Task Descriptor List Base Address


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808400`	`0x10808420`

Size: 32

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`CQTDLBA` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`CQTDLBA` `RW 0x0`

CQRS08 Fields

Bit Name Description Access Reset

31:0

Bit	Name	Description	Access	Reset
31:0	`CQTDLBA`	CQTDLBA - Task Descriptor List Base Address (lower)\n Base address (32 lower bits) of the Task Descriptor List. S/W will write values aligned to 1kB boundary (lower 10 bits have to be 0). The hardware ignores 10 lower bits.\n S/W will update this register only when CQE is disabled.	`RW`	`0x0`

CQTDLBA

              CQTDLBA - Task Descriptor List Base Address (lower)\n
              Base address (32 lower bits) of the Task Descriptor List.
              S/W will write values aligned to 1kB boundary (lower 10 bits have to be 0).
              The hardware ignores 10 lower bits.\n
              S/W will update this register only when CQE is disabled.

RW

0x0