CQRS07 

         
            CQRS07 - Interrupt Coalescing\n
            This register allows to group a CQ transfer and report single interrupt for entire group of requested tasks.
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x1080841C

Size: 32

Offset: 0x1C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CQICED

RW 0x0

Reserved_6

RO 0x0

CQICSB

RO 0x0

Reserved_5

RO 0x0

CQICCTR

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CQICCTHWEN

WO 0x0

Reserved_3

RO 0x0

CQICCTH

RW 0x0

CQICTOVALEN

WO 0x0

CQICTOVAL

RW 0x0

CQRS07 Fields

Bit Name Description Access Reset
31 CQICED 
              CQICED - Interrupt Coalescing Enable/Disable\n
              Enables coalescing mechanism allowing to generate coalescing interrupts.
RW 0x0
30:21 Reserved_6 
Reserved bitfield added by Magillem
 RO 0x0
20 CQICSB 
              CQICSB - Interrupt Coalescing Status Bit (ICSB)\n
              CQE sets this bit 1 when any task with INT=0 is completed.
RO 0x0
19:17 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
16 CQICCTR 
              CQICCTR - Counter and Timer Reset(ICCTR)\n
              S/W resets interrupt coalescing timer and counter.
WO 0x0
15 CQICCTHWEN 
              CQICCTHWEN - Interrupt Coalescing Counter Threshold Write Enable (ICCTHWEN)\n
              This is write enable for CQICCTH. When this bit is set 1, the field will be updated.
WO 0x0
14:13 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
12:8 CQICCTH 
              CQICCTH - Interrupt Coalescing Counter Threshold (ICCTH)\n
              CQE increments internal counter when task with INT=0 is completed. When internal counter reaches this value the coalescing generates interrupt.
              S/W can select treshold value in range 1 to 31.
              S/W can disable internal counter and interrupt generation by setting this field to 0.
RW 0x0
7 CQICTOVALEN 
              CQICTOVALEN - Interrupt Coalescing Timeout Value Write Enable (ICTOVALWEN)\n
              This is write enable for CQICTOVAL. When this bit is set 1, the field will be updated.
WO 0x0
6:0 CQICTOVAL 
              CQICTOVAL - Interrupt Coalescing Timeout Value (ICTOVAL)\n
              CQE generates interrupt when internal counter reaches period defined in this field. The counter starts when first transfer with INT=0 is completed.
              The counter increments each time when Internal Clock * 1024 period elapsed. S/W can disable this timer by setting this filed to 0.
RW 0x0