CQRS05 

         
            CQRS05 - Command Queuing Interrupt Status Enable\n
            Statuses Enable bits enables interrupt sources. The status is enabled when bit is set 1 (S/W wrote 1 to the field).
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x10808414

Size: 32

Offset: 0x14

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_4

RO 0x0

CQTCLST

RW 0x0

CQREDST

RW 0x0

CQTCCST

RW 0x0

CQHACST

RW 0x0

CQRS05 Fields

Bit Name Description Access Reset
31:4 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
3 CQTCLST 
              CQTCLST - Task Cleared Status Enable (TCL)\n
              Enables CQTCL register.
RW 0x0
2 CQREDST 
              CQREDST - Response Error Detected Status Enable (RED)\n
              Enables CQREDI register.
RW 0x0
1 CQTCCST 
              CQTCCST - Task Complete Status Enable (TCC)\n
              Enables CQHAC register.
RW 0x0
0 CQHACST 
              CQHACST - Halt Complete Status Enable (HAC)\n
              Enables CQTCLST register.
RW 0x0