CQRS03 

         CQRS03 - Command Queuing Control
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x1080840C

Size: 32

Offset: 0xC

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_2

RO 0x0

CQCAT

RW 0x0

Reserved_1

RO 0x0

CQHLT

RW 0x0

CQRS03 Fields

Bit Name Description Access Reset
31:9 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
8 CQCAT 
              CQCAT - Clear All Tasks\n
              Clears (1) all active tasks in the host controller. Software has to poll this register until operation is completed (bit is automatically cleared).
              Software can set this bit only when the CQ Engine is halted. Software has to clear all requested tasks in the eMMC device. Writing (0) has no effect.
RW 0x0
7:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 CQHLT 
              CQHLT - Halt CQ\n
              Engine can be halted by writing this bit 1.
              Any pending operation will be completed, and awaiting operation will be stopped. Once all tasks are completed or stopped this bit is set 1.
              The host controller will not automatically start any new operation, but software can use SRS registers to issue any command directly bypassing CQE.
              CQ Engine starts operation after being halted by writing 0 to this register. Writing 0 is ignored when CQ Engine is not halted.
RW 0x0