CQRS02 

         CQRS02 - Command Queuing Configuration
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x10808408

Size: 32

Offset: 0x8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_3

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_3

RO 0x0

CQDCE

RW 0x0

Reserved_2

RO 0x0

CQTDS

RW 0x0

Reserved_1

RO 0x0

CQE

RW 0x0

CQRS02 Fields

Bit Name Description Access Reset
31:13 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
12 CQDCE 
              CQDCE - Direct Command (DCMD) Enable\n
              Process Task Descriptor for slot 31 as Data Transfer Task Descriptor (0) or Direct Command Task Descriptor (1).
RW 0x0
11:9 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
8 CQTDS 
              CQTDS - Task Descriptor\n
              Size Expect 128 bit (1) or 64 bit (0) task descriptor. This setting can be changed only when Command Queuing is disabled (CQE = 0).
RW 0x0
7:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 CQE 
              CQE - Command Queuing Enable\n
              Enables (1) or disables (0) the Command Queuing.
              This bit can be enabled only when all previous transactions are completed. This bit can be cleared only when all tasks are completed or cleared.\n

              Setting this bit to 1, set SRS15.HV4E automatically to 1.
RW 0x0