CQRS01
CQRS01 - Command Queuing Capabilities
Module Instance | Base Address | Register Address |
---|---|---|
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000
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0x10808400
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0x10808404
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Size: 32
Offset: 0x4
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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CQRS01 Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:16 |
Reserved_2
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
15:12 |
ITCFMUL
|
ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL)\n Defines multiplier of internal clock frequency for the coalescing timer and for the SQS polling period.\n 0 - 0.001 MHz\n 1 - 0.01 MHz\n 2 - 0.1 MHz\n 3 - 1 MHz\n 4 - 10 MHz\n The ITCFMUL and ITCFVAL defines the clock frequency. |
RO
|
0x0
|
11:10 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
9:0 |
ITCFVAL
|
ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL)\n Value defines internal clock frequency for the coalescing timer and for the SQS polling period. The frequency is equal to ITCFMUL * ITCFVAL. |
RO
|
0x0
|