DMIUUESR

         DMIU Uncorrectable Error Status Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_DMI0`	`0x1C007000`	`0x1C007108`

Size: 32

Offset: 0x108

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ErrInfo` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd2` `RO 0x0`								`ErrType` `RO 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`

DMIUUESR Fields


Bit	Name	Description	Access	Reset
31:16	`ErrInfo`	This field indicates additional information about logged error type, if the Uncorrectable Error Valid bit is set. If it is a data SRAM uncorrectable error then bits 1:0 2'b10 represent write buffer (2'b00, 2'b01 and 2'b11: reserved) bits 15:2 Reserved If it is a cache SRAM uncorrectable error then bit 0 1'b0 Tag Array 1'b1 Data Array bits 15:1 Reserved If it is a native interface write response error then bits 1:0 Response from the interface bit 2 Security attirbute bit 3 If set then it was an eviction else write bits 15:4 Reserved If it is a native interface read response error then bits 1:0 Response from the interface bit 2 Security attirbute bit 3 If set then it was an fill else read without fill bits 15:4 Reserved If it is a transport error then bit 0 1'b0 represents wrong target ID; 1'b1 Reserved bits 5:1 Reserved bits 15:6 Represents source ID If it is a time out error then bits 1:0 Reserved bit 2 Represents the security bit bits 15:3 Reserved	`RO`	`0x0`
15:8	`Rsvd2`	Reserved	`RO`	`0x0`
7:4	`ErrType`	This field indicates the logged error type, if the Uncorrectable Error Valid bit is set. 0x00: Data SRAM uncorrectable error 0x01: Cache SRAM uncorrectable error 0x02: Native interface write response error 0x03: Native interface read response error 0x08: Transport error 0x09: Timeout error All other encodings are reserved	`RO`	`0x0`
3:1	`Rsvd1`	Reserved	`RO`	`0x0`
0	`ErrVld`	If this bit is set, Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit.	`RW`	`0x0`