DMIUUEIR

         DMIU Uncorrectable Error Interrupt Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_DMI0`	`0x1C007000`	`0x1C007104`

Size: 32

Offset: 0x104

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd2` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd2` `RO 0x0`											`TimeoutErrIntEn` `RW 0x0`	`Rsvd1` `RO 0x0`	`MemErrIntEn` `RW 0x0`	`TransErrIntEn` `RW 0x0`	`ProtErrIntEn` `RW 0x0`

DMIUUEIR Fields


Bit	Name	Description	Access	Reset
31:5	`Rsvd2`	Reserved	`RO`	`0x0`
4	`TimeoutErrIntEn`	Timeout uncorrectable error interrupt enable.	`RW`	`0x0`
3	`Rsvd1`	Reserved	`RO`	`0x0`
2	`MemErrIntEn`	SRAM memory uncorrectable error interrupt enable.	`RW`	`0x0`
1	`TransErrIntEn`	Concerto Transport uncorrectable error interrupt enable.	`RW`	`0x0`
0	`ProtErrIntEn`	Downstream AXI uncorrectable error interrupt enable.	`RW`	`0x0`