DMIUSMCMCR 

         DMIU System Memory Cache Maintenance Control Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__CCU_DMI0 0x1C007000 0x1C007340

Size: 32

Offset: 0x340

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Rsvd2

RO 0x0

SecAttr

RW 0x0

ArrayID

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rsvd1

RO 0x0

MntOp

RW 0x0

DMIUSMCMCR Fields

Bit Name Description Access Reset
31:23 Rsvd2 
Reserved
 RO 0x0
22 SecAttr 
This bit indicates the value of the security attribute of the address for the cache maintenance operation is to be performed. 
            If the cache maintenance operation does not operate on an address, the value of this bit should be zero.
 RW 0x0
21:16 ArrayID 
This field selects the array on which the cache maintenance operation is to be performed:
              0x00: Tag Array 
              0x01: Data Array
              0x02-0x3F: Reserved
 RW 0x0
15:4 Rsvd1 
Reserved
 RO 0x0
3:0 MntOp 
This field encodes the cache maintenance operation to be performed:
            0x0: Initialize all Entries
            0x1-0x3: Reserved
            0x4: Flush All Entries
            0x5: Flush Entry at Set and Way
            0x6: Flush Entry at Address
            0x7: Flush Address Range
            0x8: Flush Set Way Range
            0x9-0xB: Reserved
            0xC: Debug Read Entry at set, way, and word
            0xD: Reserved
            0xE: Debug Write Entry at set, way, and word
            0xF: Reserved
 RW 0x0