DMA_CH4_Tx_Control

         The DMA Channel4 Transmit Control register controls the Tx features such as PBL, TCP segmentation, and Tx Channel weights.


Module Instance	Base Address	Register Address
`u_emac0__apb_reg_config_slave__10810000__DWCXG_DMA_CH4__SEG_L4_MP_emac0_s_0x0_0x10000`	`0x10813300`	`0x10813304`

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31` `RO 0x0`	`TFSEL` `RW 0x0`		`Reserved_EDSE` `RO 0x0`	`TQOS` `RW 0x0`				`Reserved_23_22` `RO 0x0`		`TxPBL` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_IPBL` `RO 0x0`	`Reserved_14_13` `RO 0x0`		`Reserved_TSE` `RO 0x0`	`Reserved_11_5` `RO 0x0`							`Reserved_OSP` `RO 0x0`	`Reserved_3_1` `RO 0x0`			`ST` `RW 0x0`

DMA_CH4_Tx_Control Fields

Bit Name Description Access Reset

Reserved_31

Reserved.

RO

0x0

30:29

TFSEL

TBS Fetch Time Select.
  
   Select bits for one of the four DMA_TBS_CTRL register fields (FTOS,FGSN,FTOV) for the channel.
  
   Note:  If Configured Transmit DMA channels are less or equal to 4 then this field is reserved and one to one DMA_TBS_CTRL(#i) register mapping is
  used for each Channel. Example: DMA_TBS_CTRL0 is used for Channel 0, DMA_TBS_CTRL1 is used for Channel 1, and so on.

Value	Description
0x0	DMA_TBS_CTRL0
0x1	DMA_TBS_CTRL1
0x2	DMA_TBS_CTRL2
0x3	DMA_TBS_CTRL3

RW

0x0

Reserved_EDSE

Reserved.

RO

0x0

27:24

TQOS

Transmit QOS.
  
  This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel4.

RW

0x0

23:22

Reserved_23_22

Reserved.

RO

0x0

21:16

TxPBL

Transmit Programmable Burst Length.
  
  These bits indicate the maximum number of beats to be transferred in one DMA data transfer. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior.
  
  To transfer more than 32 beats, perform the following steps:
   - Set the PBLx8 mode in DMA_CH4_Control register.
   - Set the PBL.
  Note-1: This PBL is for the internal DMA engine. The AXI Interface block can split this PBL requests from DMA engine into multiple AXI requests based on the programmed values in DMA_SysBus_Mode register. 
  
  Note-2: The maximum limit is equal to half of the Tx Queue depth (Queue Depth = Queue Size / Datawidth)

RW

0x0

Reserved_IPBL

Reserved.

RO

0x0

14:13

Reserved_14_13

Reserved.

RO

0x0

Reserved_TSE

Reserved.

RO

0x0

11:5

Reserved_11_5

Reserved.

RO

0x0

Reserved_OSP

Reserved.

RO

0x0

3:1

Reserved_3_1

Reserved.

RO

0x0

ST

Start or Stop Transmission Command.
  
  When this bit is set, transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted.
  
  The DMA tries to acquire descriptor from either of the following positions:
   - The current position in the list
  This is the base address of the Transmit list set by the DMA_CH4_TxDesc_List_LAddress register.
   - The position at which the transmission was previously stopped
  If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the DMA_CH4_Status register is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the DMA_CH4_TxDesc_List_LAddress register, the DMA behavior is unpredictable.
  
  When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, program DMA_CH4_TxDesc_List_Address register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state.

RW

0x0