NAND_ctb_Rfile Address Map


Module Instance	Base Address	End Address
`i_nand__reg_apb__10b80000__ctb_Rfile__SEG_L4_MP_nand_s_0x0_0x10000`	`0x10B82080`	`0x10B8210B`


Register	Offset	Width	Access	Reset Value	Description
`phy_ctrl_reg`	`0x0`	`32`	`RO`	`0x00004310`	This register handles the global control settings for the PHY.
`phy_tsel_reg`	`0x4`	`32`	`RO`	`0x00000000`	This register handles the global control settings for the termination selects for reads. For SD controllers this should be disabled.
`phy_gpio_ctrl_0`	`0x8`	`32`	`RW`	`0x00000000`	Reserved.
`phy_gpio_ctrl_1`	`0xC`	`32`	`RW`	`0x00000000`	Reserved.
`phy_gpio_status_0`	`0x10`	`32`	`RO`	`0x00000000`	Reserved.
`phy_gpio_status_1`	`0x14`	`32`	`RO`	`0x00000000`	Reserved.