ECC_DECODERSTAT 

         <p>Individual decoder flags for single and double bits errors.</p>
<p>Each decoder flags used represent one decoder in the design.</p>
Module Instance Base Address Register Address
ecc_usbotg0__ecc_csr__108c4000__ecc_registerBlock__SEG_L4_ECC_usb0_ecc_0x0_0x400 0x108C4000 0x108C4084 - 0x108C417E

Size: 32

Offset: 0x84

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_16

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DEC7DERRFLG

RW 0x0

DEC6DERRFLG

RW 0x0

DEC5DERRFLG

RW 0x0

DEC4DERRFLG

RW 0x0

DEC3DERRFLG

RW 0x0

DEC2DERRFLG

RW 0x0

DEC1DERRFLG

RW 0x0

DEC0DERRFLG

RW 0x0

DEC7SERRFLG

RW 0x0

DEC6SERRFLG

RW 0x0

DEC5SERRFLG

RW 0x0

DEC4SERRFLG

RW 0x0

DEC3SERRFLG

RW 0x0

DEC2SERRFLG

RW 0x0

DEC1SERRFLG

RW 0x0

DEC0SERRFLG

RW 0x0

ECC_DECODERSTAT Fields

Bit Name Description Access Reset
31:16 Reserved_16 
Reserved bitfield added by Magillem
 RO 0x0
15 DEC7DERRFLG 
This bit indicates decoder(*) has detected double-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
14 DEC6DERRFLG 
This bit indicates decoder(*) has detected double-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
13 DEC5DERRFLG 
This bit indicates decoder(*) has detected double-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
12 DEC4DERRFLG 
This bit indicates decoder(*) has detected double-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
11 DEC3DERRFLG 
This bit indicates decoder(*) has detected double-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
10 DEC2DERRFLG 
This bit indicates decoder(*) has detected double-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
9 DEC1DERRFLG 
This bit indicates decoder(*) has detected double-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
8 DEC0DERRFLG 
This bit indicates decoder(*) has detected double-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
7 DEC7SERRFLG 
This bit indicates deocder(*) has detected single-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
6 DEC6SERRFLG 
This bit indicates deocder(*) has detected single-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
5 DEC5SERRFLG 
This bit indicates deocder(*) has detected single-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
4 DEC4SERRFLG 
This bit indicates deocder(*) has detected single-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
3 DEC3SERRFLG 
This bit indicates deocder(*) has detected single-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
2 DEC2SERRFLG 
This bit indicates deocder(*) has detected single-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
1 DEC1SERRFLG 
This bit indicates deocder(*) has detected single-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0
0 DEC0SERRFLG 
This bit indicates deocder(*) has detected single-bit error.
1'b0: No error has been captured with this flag
1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware and it will be cleared by writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This wont be reset by the ecc_en bit. Number of decoders implemented is IP dependent.
 RW 0x0