ERRINTENS

         Error interrupt set


Module Instance	Base Address	Register Address
`ecc_usb1_tx__ecc_csr__108c4800__ecc_registerBlock__SEG_L4_ECC_usb1_txecc_0x0_0x400`	`0x108C4800`	`0x108C4814 - 0x108C486C`

Size: 32

Offset: 0x14

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`															`SERRINTS` `RW 0x0`

ERRINTENS Fields


Bit	Name	Description	Access	Reset
31:1	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
0	`SERRINTS`	This bit is used to enable ERRINTENS.SERRINTEN field	`RW`	`0x0`