INTTEST

         This bits is used to test interrupt from ECC RAM to GIC


Module Instance	Base Address	Register Address
`ecc_usb1_cache__ecc_csr__108c4c00__ecc_registerBlock__SEG_L4_ECC_usb1_cacheecc_0x0_0x400`	`0x108C4C00`	`0x108C4C24 - 0x108C4C82`

Size: 32

Offset: 0x24

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_4` `RO 0x0`							`TDERRB` `RW 0x0`	`Reserved_3` `RO 0x0`							`TSERRB` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_2` `RO 0x0`							`TDERRA` `RW 0x0`	`Reserved_1` `RO 0x0`							`TSERRA` `RW 0x0`

INTTEST Fields


Bit	Name	Description	Access	Reset
31:25	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
24	`TDERRB`	Test PORTB Double-bit error.	`RW`	`0x0`
23:17	`Reserved_3`	Reserved bitfield added by Magillem	`RO`	`0x0`
16	`TSERRB`	Test PORTB Single-bit error.	`RW`	`0x0`
15:9	`Reserved_2`	Reserved bitfield added by Magillem	`RO`	`0x0`
8	`TDERRA`	Test PORTA Double-bit error.	`RW`	`0x0`
7:1	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
0	`TSERRA`	Test PORTA Single-bit error.	`RW`	`0x0`