ERRINTEN
Error Interrupt enable
| Module Instance | Base Address | Register Address |
|---|---|---|
ecc_usb1_cache__ecc_csr__108c4c00__ecc_registerBlock__SEG_L4_ECC_usb1_cacheecc_0x0_0x400
|
0x108C4C00
|
0x108C4C10 - 0x108C4C62
|
Size: 32
Offset: 0x10
Access: RW
Access mode: PRIVILEGEMODE
Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
|
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
|
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ERRINTEN Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:1 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
||||||
| 0 |
SERRINTEN
|
This bit is used to enable single bit error interrupt of ECC RAM system
|
RW
|
0x0
|