di_control 

         Register provided to control the data integrity feature.
Module Instance Base Address Register Address
i_nand__reg_apb__10b80000__rf_di_regs__SEG_L4_MP_nand_s_0x0_0x10000 0x10B80700 0x10B80700

Size: 32

Offset: 0x

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_5

RO 0x0

di_inj_type

RW 0x0

Reserved_4

RO 0x0

di_type

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

di_par_rsp_en

RW 0x0

Reserved_2

RO 0x0

di_crc_en

RW 0x0

di_parity_en

RW 0x0

di_control Fields

Bit Name Description Access Reset
31:25 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
24 di_inj_type 
Injection type: 0-one time injection, 1-continuous injection.
 RW 0x0
23:17 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
16 di_type 
DI type: 0-even, 1-odd.
 RW 0x0
15 di_par_rsp_en 
Enable error response generation on SFR interface when parity error detected.
 RW 0x0
14:2 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
1 di_crc_en 
Enable CRC checking.
 RW 0x0
0 di_parity_en 
Enable parity checking.
 RW 0x0