lwsoc2fpga 

         Per-Master Security bit for Lightweight SOC2FPGA
Module Instance Base Address Register Address
noc_fw_lwsoc2fpga__ocp_slv__10d21300__lwsoc2fpga_scr 0x10D21300 0x10D21300

Size: 32

Offset: 0x

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_14

RO 0x0

sdm_nand

RW 0x0

sdm_sdmmc

RW 0x0

etr

RW 0x0

axi_ap

RW 0x0

nand

RW 0x0

sdmmc

RW 0x0

usb1

RW 0x0

usb0

RW 0x0

emac2

RW 0x0

emac1

RW 0x0

emac0

RW 0x0

Reserved_3

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_3

RO 0x0

dmam1

RW 0x0

dmam0

RW 0x0

Reserved_1

RO 0x0

mpu

RW 0x0

lwsoc2fpga Fields

Bit Name Description Access Reset
31:28 Reserved_14 
Reserved bitfield added by Magillem
 RO 0x0
27 sdm_nand 
Security bit configuration for transactions from SDM NAND to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
26 sdm_sdmmc 
Security bit configuration for transactions from SDM SDMMC to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
25 etr 
Security bit configuration for transactions from etr to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
24 axi_ap 
Security bit configuration for transactions from axi_ap to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
23 nand 
Security bit configuration for transactions from nand to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
22 sdmmc 
Security bit configuration for transactions from sdmmc to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
21 usb1 
Security bit configuration for transactions from usb1 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
20 usb0 
Security bit configuration for transactions from usb0 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
19 emac2 
Security bit configuration for transactions from emac2 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
18 emac1 
Security bit configuration for transactions from emac1 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
17 emac0 
Security bit configuration for transactions from emac0 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
16:10 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
9 dmam1 
Security bit configuration for transactions from dmam1 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
8 dmam0 
Security bit configuration for transactions from dma0 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
7:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 mpu 
Security bit configuration for transactions from mpu to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0