INTR_STATUS 

         
Interrupt Status Register
Module Instance Base Address Register Address
i_i3c_secondary_master__i3c_s_apb_slv__10da1000__DWC_mipi_i3c_block__SEG_L4_SP_i3c1_0x0_0x1000 0x10DA1000 0x10DA103C

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_13

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_13

RO 0x0

BUSOWNER_UPDATED_STS

RW 0x0

IBI_UPDATED_STS

RW 0x0

READ_REQ_RECV_STS

RW 0x0

DEFSLV_STS

RW 0x0

TRANSFER_ERR_STS

RW 0x0

DYN_ADDR_ASSGN_STS

RW 0x0

Reserved_7

RO 0x0

CCC_UPDATED_STS

RW 0x0

TRANSFER_ABORT_STS

RW 0x0

RESP_READY_STS

RO 0x0

CMD_QUEUE_READY_STS

RO 0x0

IBI_THLD_STS

RO 0x0

RX_THLD_STS

RO 0x0

TX_THLD_STS

RO 0x0

INTR_STATUS Fields

Bit Name Description Access Reset
31:14 Reserved_13 
Reserved bitfield added by Magillem
 RO 0x0
13 BUSOWNER_UPDATED_STS 
This interrupt is set when the role of the controller changes from being a Master to Slave or vice versa.

This bit can be cleared by writing 1'b1.
RW 0x0
12 IBI_UPDATED_STS 
IBI status is updated.

This field is used only in slave mode of operation.

It indicates that the IBI request initiated through SIR request register is addressed and status is updated.
RW 0x0
11 READ_REQ_RECV_STS 
Read Request Received.

This field is used only in slave mode of operation.

Read Request received from the current master when CMDQ is empty. This bit can be cleared by writing 1'b1.
RW 0x0
10 DEFSLV_STS 
Define Slave CCC Received Status. 

This interrupt is generated if DEFSLV  CCC is received.

This bit can be cleared by writing 1'b1.
RW 0x0
9 TRANSFER_ERR_STS 
Transfer Error Status. 

This interrupt is generated if any error occurs during transfer. The error type is specified in
the response packet associated with the command (in ERR_STATUS field of RESPONSE_QUEUE_PORT register).
This bit can be cleared by writing 1'b1.
RW 0x0
8 DYN_ADDR_ASSGN_STS 
Dynamic Address Assigned Status. 

This field is used only in slave mode of operation.

This interrupt is generated if the device's Dynamic Address is assigned through SETDASA or ENTDAA CCC.
This bit can be cleared by writing 1'b1.
RW 0x0
7 Reserved_7 
Reserved bitfield added by Magillem
 RO 0x0
6 CCC_UPDATED_STS 
CCC Table Updated Status. 

This field is used only in slave mode of operation.

This interrupt is generated if any of the CCC registers are updated by I3C Master through CCC commands.
This interrupt can be cleared by writing 1'b1.
RW 0x0
5 TRANSFER_ABORT_STS 
Transfer Abort Status.

This field is used only in master mode of operation.

This interrupt is generated if transfer is aborted. This interrupt can be cleared by writing 1'b1.
RW 0x0
4 RESP_READY_STS 
Response Queue Ready Status.

This interrupt is generated when number of entries in response queue is greater than or equal to threshold value
specified by RESP_BUF_THLD field in QUEUE_THLD_CTRL register. This interrupt is cleared automatically when
number of entries in response buffer is less than threshold value specified.
RO 0x0
3 CMD_QUEUE_READY_STS 
Command Queue Ready. 

This interrupt is generated when number of empty locations in command queue is greater than or equal to threshold
value specified by CMD_EMPTY_BUF_THLD field in QUEUE_THLD_CTRL register. This interrupt is cleared automatically
when number of empty locations in command buffer is less than threshold value specified.
RO 0x0
2 IBI_THLD_STS 
IBI Buffer Threshold Status. 

This field is only used in master mode of operation
This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value
specified by IBI_BUF_THLD field in QUEUE_THLD_CTRL register. This interrupt is cleared automatically
when number of entries in IBI buffer is less than threshold value specified.
RO 0x0
1 RX_THLD_STS 
Receive Buffer Threshold Status. 

This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold
value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt is cleared
automatically when number of entries in receive buffer is less than threshold value specified.
RO 0x0
0 TX_THLD_STS 
Transmit Buffer Threshold Status

This interrupt is generated when the number of empty locations in transmit buffer is greater than or equal to
threshold value specified by TX_EMPTY_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt is cleared automatically when number of empty locations in transmit buffer is less than threshold value
specified.
RO 0x0