DEVICE_CTRL

Controls whether or not DWC_mipi_i3c is enabled.
 - 1: Enables the DWC_mipi_i3c controller.
 - 0: Disables the DWC_mipi_i3c controller.

In Master mode of operation, software can disable DWC_mipi_i3c while it is active.
However, the controller may not get disabled immediately and is 'Disabled' after commands in the Command queue (if any) are executed leading to a STOP condition on the bus and Master FSM is in IDLE state (as indicated by PRESENT_STATE Register). 



In Slave mode of operation, software can disable DWC_mipi_i3c while it is active. However, the disable happens after the ongoing transfer is
completed on the I3C bus. Software can read back 1'b0 from this field once disabling of DWC_mipi_i3c is completed.
After power on reset, the software can enable I3C slave controller by programming this bit to 1'b1. However, the I3C bus interface of the controller,
responds to transfer on the bus only after it observes Bus Available condition for BUS_AVAILABLE_TIME*IDLE_CNT_MULTPLIER counts of pclk period. The successful completion of Enable/Disable of the controller depends on availability of SCL to the controller at the time of performing this operation, and hence may not happen instantly.

DWC_mipi_i3c Resume

This bit is used to resume the controller after it goes to the halt state.


In the Master mode of operation, the controller goes to the halt state (as indicated in PRESENT_STATE Register) due to any type of error
in the transfer (the type of error is indicated by ERR_STATUS field in the RESPONSE_QUEUE_PORT register).

After the controller gones to the halt state, the application has to write 1'b1 to this bit to resume the controller.
This bit is auto-cleared once the controller resumes the transfers by initiating the next command.


In the Slave mode of operation, the controller goes to the halt state due to following conditions:
 - Any type of error in the transfer (the type of error is indicated by ERR_STATUS field in the RESPONSE_QUEUE_PORT register)
 - MRL Register updated by the master through SETMRL CCC.
After the controller goes to the halt state, the application has to take necessary action to handle the error condition and then write 1'b1
to this bit to resume the controller.
This bit is auto-cleared once the controller is ready to accept new transfers.

DWC_mipi_i3c Abort

This bit is used in Master mode of operation. 

This bit allows the controller to relinquish the DWC_mipi_i3c bus before completing the issued transfer.

In response to an ABORT request, the controller issues the STOP condition after the complete
data byte is transferred or received.

This bit is auto-cleared once the transfer is aborted and the controller issues a 'Transfer Abort' interrupt.

DMA Handshake Interface Enable

This bit is used to enable or disable the DMA Handshaking interface, and is applicable to both Master and Slave modes of operation. 

 - 1: Enables the DMA handshake control to interact with external DMA.

 - 0: The DMA handshake control has no significance.

This field is used in Slave mode of operation. 
Note that when mode_i2c strap is driven to '0', the Slave controller operates in Adaptive Mode. 
Setting of this bit is NOT required to put the controller in Adaptive Mode. 
It is only used  to enable some features of the Slave controller to adapt to "Adaptive I2C/I3C mode" 
of operation. This bit is cleared automatically if the controller determines the mode as I3C.
Effect on Hot-Join:
If this bit is programmed to 1'b1, the controller initiates a
Hot-Join request only after it has switched to I3C mode of operation. 
If this bit is not set, the controller initiates a Hot-Join
without determining the bus mode assuming itself to be
on DWC_mipi_i3c bus. This bit should be set only if the Slave application
does not know to which bus the device is connected to.

Reserved bitfield added by Magillem

Idle Count Multiplier

This bit is used in Slave mode of operation.

After power-on reset, the Slave controller is enabled only after it sees both SDA and SCL lines idle for a specified time.
This idle time is calculated by multipliying IDLE_CNT_MULITPLIER with BUS_AVAILABLE_TIME field in the BUS_FREE_AVAIL_TIMING register.
- 00 - BUS_AVAILABLE_TIME * 1
- 01 - BUS_AVAILABLE_TIME * 2
- 10 - BUS_AVAILABLE_TIME * 4
- 11 - BUS_AVAILABLE_TIME * 8

Reserved bitfield added by Magillem

Hot-Join ACK/NACK Control

This bit is used in master mode of operation. 

This bit acts as a global control to ACK/NACK the Hot-Join request from the devices. The DWC_mipi_i3c Master
 ACK/NACKs the Hot-Join request from other devices connected on the DWC_mipi_i3c bus, based on programming of this bit.
 - 0: ACK the Hot-join request.
 - 1: NACK and send broadcast CCC to disable Hot-Join.

I2C Slave Present

This bit is used in master mode of operation. 

This bit indicates whether any Legacy I2C devices are present in the system.

In HDR mode, this field is used to select TSL over TSP in a mixed bus configuration.

Reserved bitfield added by Magillem

I3C Broadcast Address include

This bit is used in Master mode of operation.

This bit is used to include DWC_mipi_i3c broadcast address (0x7E) for private transfer.

Note: If DWC_mipi_i3c broadcast address is not included for the private transfers, In-band Interrupts (IBI)
driven from Slaves might not win address arbitration. Hence, the IBIs get delayed.