IC_INTR_MASK 

         Name: I2C Interrupt Mask Register
Size: 15 bits
Address Offset: 0x30
Read/Write Access: Read/Write However, 
if configuration parameter IC_SLV_RESTART_DET = 0, bit 13 is read only; 
if configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0 or IC_EMPTYFIFO_HOLD_MASTER_EN = 0, bit 14 is read only.
if configuration parameter IC_BUS_CLEAR_FEATURE = 0, bit 15 is read only.
These bits mask their corresponding interrupt status bits.
They are active high; a value of 0 prevents a bit from
generating an interrupt.
Module Instance Base Address Register Address
i_i2c_0__i2c_csr__10c02800__DW_apb_i2c_addr_block1__SEG_L4_SP_i2c0_0x0_0x100 0x10C02800 0x10C02830

Size: 32

Offset: 0x30

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_INTR_STAT

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_INTR_STAT

RO 0x0

RSVD_M_SCL_STUCK_AT_LOW

RO 0x0

M_MASTER_ON_HOLD

RW 0x0

M_RESTART_DET

RW 0x0

M_GEN_CALL

RW 0x1

M_START_DET

RW 0x0

M_STOP_DET

RW 0x0

M_ACTIVITY

RW 0x0

M_RX_DONE

RW 0x1

M_TX_ABRT

RW 0x1

M_RD_REQ

RW 0x1

M_TX_EMPTY

RW 0x1

M_TX_OVER

RW 0x1

M_RX_FULL

RW 0x1

M_RX_OVER

RW 0x1

M_RX_UNDER

RW 0x1

IC_INTR_MASK Fields

Bit Name Description Access Reset
31:15 RSVD_IC_INTR_STAT 
Reserved bits - Read Only
 RO 0x0
14 RSVD_M_SCL_STUCK_AT_LOW 
Reserved bits - Read Only
 RO 0x0
13 M_MASTER_ON_HOLD 
This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.
Reset value: 0x0
Value Description
0x0 MASTER_ON_HOLD interrupt is masked
0x1 MASTER_ON_HOLD interrupt is unmasked
RW 0x0
12 M_RESTART_DET 
This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.
Reset value: 0x0
Value Description
0x0 RESTART_DET interrupt is masked
0x1 RESTART_DET interrupt is unmasked
RW 0x0
11 M_GEN_CALL 
This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.
Reset value: 0x1
Value Description
0x0 GEN_CALL interrupt is masked
0x1 GEN_CALL interrupt is unmasked
RW 0x1
10 M_START_DET 
This bit masks the R_START_DET interrupt in IC_INTR_STAT register.
Reset value: 0x0
Value Description
0x0 START_DET interrupt is masked
0x1 START_DET interrupt is unmasked
RW 0x0
9 M_STOP_DET 
This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.
Reset value: 0x0
Value Description
0x0 STOP_DET interrupt is masked
0x1 STOP_DET interrupt is unmasked
RW 0x0
8 M_ACTIVITY 
This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
Reset value: 0x0
Value Description
0x0 ACTIVITY interrupt is masked
0x1 ACTIVITY interrupt is unmasked
RW 0x0
7 M_RX_DONE 
This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x1
Value Description
0x0 RX_DONE interrupt is masked
0x1 RX_DONE interrupt is unmasked
RW 0x1
6 M_TX_ABRT 
This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.
Reset value: 0x1
Value Description
0x0 TX_ABORT interrupt is masked
0x1 TX_ABORT interrupt is unmasked
RW 0x1
5 M_RD_REQ 
This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x1
Value Description
0x0 RD_REQ interrupt is masked
0x1 RD_REQ interrupt is unmasked
RW 0x1
4 M_TX_EMPTY 
This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.
Reset value: 0x1
Value Description
0x0 TX_EMPTY interrupt is masked
0x1 TX_EMPTY interrupt is unmasked
RW 0x1
3 M_TX_OVER 
This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.
Reset value: 0x1
Value Description
0x0 TX_OVER interrupt is masked
0x1 TX_OVER interrupt is unmasked
RW 0x1
2 M_RX_FULL 
This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
Reset value: 0x1
Value Description
0x0 RX_FULL interrupt is masked
0x1 RX_FULL interrupt is unmasked
RW 0x1
1 M_RX_OVER 
This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.
Reset value: 0x1
Value Description
0x0 RX_OVER interrupt is masked
0x1 RX_OVER interrupt is unmasked
RW 0x1
0 M_RX_UNDER 
This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
Reset value: 0x1
Value Description
0x0 RX_UNDER interrupt is masked
0x1 RX_UNDER interrupt is unmasked
RW 0x1