ECC_WDataecc0bus

         The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.


Module Instance	Base Address	Register Address
`ecc_emac2_rx__ecc_csr__108c1000__ecc_registerBlock__SEG_L4_ECC_emac2rx_ecc_0x0_0x400`	`0x108C1000`	`0x108C106C - 0x108C1154`

Size: 32

Offset: 0x6C

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ECC_WDataecc3BUS` `WO 0x0`								`ECC_WDataecc2BUS` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ECC_WDataecc1BUS` `WO 0x0`								`ECC_WDataecc0BUS` `WO 0x0`

ECC_WDataecc0bus Fields


Bit	Name	Description	Access	Reset
31:24	`ECC_WDataecc3BUS`	Eccdata from the register will be written to the RAM.	`WO`	`0x0`
23:16	`ECC_WDataecc2BUS`	Eccdata from the register will be written to the RAM.	`WO`	`0x0`
15:8	`ECC_WDataecc1BUS`	Eccdata from the register will be written to the RAM.	`WO`	`0x0`
7:0	`ECC_WDataecc0BUS`	Eccdata from the register will be written to the RAM.	`WO`	`0x0`