SERRCNTREG

         Maximum counter value for single-bit error interrupt


Module Instance	Base Address	Register Address
`ecc_emac1_rx__ecc_csr__108c0800__ecc_registerBlock__SEG_L4_ECC_emac1rx_ecc_0x0_0x400`	`0x108C0800`	`0x108C083C - 0x108C08AC`

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`SERRCNT` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`SERRCNT` `RW 0x0`

SERRCNTREG Fields


Bit	Name	Description	Access	Reset
31:0	`SERRCNT`	Counter value	`RW`	`0x0`