INTSTAT

         This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled, serr_req signal will be asserted.


Module Instance	Base Address	Register Address
`ecc_emac0_tx__ecc_csr__108c0400__ecc_registerBlock__SEG_L4_ECC_emac0tx_ecc_0x0_0x400`	`0x108C0400`	`0x108C0420 - 0x108C047E`

Size: 32

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_4` `RO 0x0`							`DERRPENB` `RW 0x0`	`Reserved_3` `RO 0x0`							`SERRPENB` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_2` `RO 0x0`							`DERRPENA` `RW 0x0`	`Reserved_1` `RO 0x0`							`SERRPENA` `RW 0x0`

INTSTAT Fields


Bit	Name	Description	Access	Reset
31:25	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
24	`DERRPENB`	Double-bit error pending PORTB.	`RW`	`0x0`
23:17	`Reserved_3`	Reserved bitfield added by Magillem	`RO`	`0x0`
16	`SERRPENB`	Single-bit error pending for PORTB.	`RW`	`0x0`
15:9	`Reserved_2`	Reserved bitfield added by Magillem	`RO`	`0x0`
8	`DERRPENA`	Double-bit error pending for PORTA.	`RW`	`0x0`
7:1	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
0	`SERRPENA`	Single-bit error pending for PORTA.	`RW`	`0x0`