DVEUENGDBR

         DVE Engineering Debug Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__dve0`	`0x1C00E000`	`0x1C00EFF0`

Size: 32

Offset: 0xFF0

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd1` `RO 0x0`															`MaxOneSyncDVMOp` `RW 0x0`

DVEUENGDBR Fields

Bit Name Description Access Reset

31:1

Bit	Name	Description	Access	Reset
31:1	`Rsvd1`	Reserved	`RO`	`0x0`
0	`MaxOneSyncDVMOp`	This bit when 0 restricts maximum outstanding Sync DVMOp to 3, when 1 restricts maximum outstanding Sync DVMOp to 1. Because 1 STT entry is always reserved for Non-Sync DVM Bypass, therefore this bit when 0 enables 3 + 1 = 4 STT entries, when 1 enables 1 + 1 = 2 STT entries.	`RW`	`0x0`

Rsvd1

Reserved

RO

0x0

MaxOneSyncDVMOp

This bit when 0 restricts maximum outstanding Sync DVMOp to 3, when 1 restricts maximum outstanding Sync DVMOp to 1. Because 1 STT entry is always reserved for Non-Sync DVM Bypass, therefore this bit when 0 enables 3 + 1 = 4 STT entries, when 1 enables 1 + 1 = 2 STT entries.

RW

0x0