DCEUCECR

         DCEU Correctable Error Control Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__dce0`	`0x1C005000`	`0x1C005100`

Size: 32

Offset: 0x100

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd2` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd2` `RO 0x0`				`ErrThreshold` `RW 0x0`								`Rsvd1` `RO 0x0`		`ErrIntEn` `RW 0x0`	`ErrDetEn` `RW 0x0`

DCEUCECR Fields


Bit	Name	Description	Access	Reset
31:12	`Rsvd2`	Reserved	`RO`	`0x0`
11:4	`ErrThreshold`	This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted.	`RW`	`0x0`
3:2	`Rsvd1`	Reserved	`RO`	`0x0`
1	`ErrIntEn`	If this bit is set, the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise, the correctable error interrupt signal is never asserted.	`RW`	`0x0`
0	`ErrDetEn`	If this bit is set, then correctable error detection and logging is enabled; otherwise, correctable error detection and logging is disabled.	`RW`	`0x0`