DCEUAMIGR

         Active Memory Interleave Group Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__dce0`	`0x1C005000`	`0x1C0053C0`

Size: 32

Offset: 0x3C0

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd1` `RO 0x0`											`AMIGS` `RW 0x0`				`Valid` `RW 0x0`

DCEUAMIGR Fields

Bit Name Description Access Reset

31:5

Bit	Name	Description	Access	Reset
31:5	`Rsvd1`	Reserved	`RO`	`0x0`
4:1	`AMIGS`	Active Memory Interleave Group Set in use currenlty when Valid is set	`RW`	`0x0`
0	`Valid`	Memory Interleave Group Set valid, when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default	`RW`	`0x0`

Rsvd1

Reserved

RO

0x0

4:1

AMIGS

Active Memory Interleave Group Set in use currenlty when Valid is set

RW

0x0

Valid

Memory Interleave Group Set valid, when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default

RW

0x0