XAIUTUBMR0

         XAIU Trace Trigger User Bits Mask Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__TCU`	`0x1C003000`	`0x1C00381C`

Size: 32

Offset: 0x81C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`user_mask` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`user_mask` `RW 0x0`

XAIUTUBMR0 Fields


Bit	Name	Description	Access	Reset
31:0	`user_mask`	User bits. Width parameterized.	`RW`	`0x0`