XAIUCCTRLR 

         XAIU Capture Control Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__TCU 0x1C003000 0x1C003900

Size: 32

Offset: 0x900

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

inc

RW 0x100

gain

RW 0x2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rsvd

RO 0x0

dn0Rx

RW 0x0

dn0Tx

RW 0x0

ndn2Rx

RW 0x0

ndn2Tx

RW 0x0

ndn1Rx

RW 0x0

ndn1Tx

RW 0x0

ndn0Rx

RW 0x0

ndn0Tx

RW 0x0

XAIUCCTRLR Fields

Bit Name Description Access Reset
31:20 inc 
Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001,8'b0000_0000}
 RW 0x100
19:16 gain 
Gain Value. 4 bit gain value for timestamp correction.
 RW 0x2
15:8 Rsvd 
Reserved
 RO 0x0
7 dn0Rx 
Dn0 SMI Rx snoop and capture enable
 RW 0x0
6 dn0Tx 
Dn0 SMI Tx snoop and capture enable
 RW 0x0
5 ndn2Rx 
Ndn2 SMI Rx snoop and capture enable
 RW 0x0
4 ndn2Tx 
Ndn2 SMI Tx snoop and capture enable
 RW 0x0
3 ndn1Rx 
Ndn1 SMI Tx snoop and capture enable
 RW 0x0
2 ndn1Tx 
Ndn1 SMI Tx snoop and capture enable
 RW 0x0
1 ndn0Rx 
Ndn0 SMI Rx snoop and capture enable
 RW 0x0
0 ndn0Tx 
Ndn0 SMI Tx snoop and capture enable
 RW 0x0