TIMERSRAWINTSTAT

         Name: Timers Raw Interrupt Status Register
Size: 1-8 bits
Address Offset: 0xa8
Read/Write Access: Read


Module Instance	Base Address	Register Address
`i_timer_sp_1__timer_csr__10c03100__DW_apb_timers_addr_block__SEG_L4_SP_timer1_0x0_0x100`	`0x10C03100`	`0x10C031A8`

Size: 32

Offset: 0xA8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`															`TIMERSRAWINTSTAT` `RO 0x0`

TIMERSRAWINTSTAT Fields

Bit Name Description Access Reset

31:1

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

TIMERSRAWINTSTAT

The register contains the unmasked interrupt status of all timers in
the component.
0 = either timer_intr or timer_intr_n is not active prior to masking
1 = either timer_intr or timer_intr_n is active prior to masking.

Value	Description
0x0	Raw Timer_intr(_n) is inactive
0x1	Raw Timer_intr(_n) is active

RO

0x0