TIMERSEOI

         Name: Timers End-of-Interrupt Register
Size: 1-8 bits
Address Offset: 0xa4
Read/Write Access: Read


Module Instance	Base Address	Register Address
`i_timer_sp_1__timer_csr__10c03100__DW_apb_timers_addr_block__SEG_L4_SP_timer1_0x0_0x100`	`0x10C03100`	`0x10C031A4`

Size: 32

Offset: 0xA4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`															`TIMERSEOI` `RO 0x0`

TIMERSEOI Fields


Bit	Name	Description	Access	Reset
31:1	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
0	`TIMERSEOI`	Reading this register returns all zeroes (0) and clears all active interrupts.	`RO`	`0x0`