TIMER1CONTROLREG

         Name: Timer1 Control Register
  Size: 4 bits
  Address Offset: 8
  Read/Write Access: Read/Write
  This register controls enabling, operating mode (free-running or defined-count), and interrupt mask of
  Timer1. You can program each Timer1ControlReg to enable or disable a specific timer and to control
  its mode of operation.


Module Instance	Base Address	Register Address
`i_timer_sp_1__timer_csr__10c03100__DW_apb_timers_addr_block__SEG_L4_SP_timer1_0x0_0x100`	`0x10C03100`	`0x10C03108`

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_3` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_3` `RO 0x0`													`TIMER_INTERRUPT_MASK` `RW 0x0`	`TIMER_MODE` `RW 0x0`	`TIMER_ENABLE` `RW 0x0`

TIMER1CONTROLREG Fields

Bit Name Description Access Reset

31:3

Reserved_3

Reserved bitfield added by Magillem

RO

0x0

TIMER_INTERRUPT_MASK

Timer interrupt mask for Timer1.
  0: not masked
  1: masked

Value	Description
0x0	Timer1 interrupt is unmasked
0x1	Timer1 interrupt is masked

RW

0x0

TIMER_MODE

Timer mode for Timer1.
  0: free_running mode
  1: user_defined count mode
  NOTE: You must set the Timer1LoadCount register to all 1s before
  enabling the timer in free-running mode.

Value	Description
0x0	Free Running mode of operation
0x1	User-Defined mode of operation

RW

0x0

TIMER_ENABLE

Timer enable bit for Timer1.
  0: disable 
  1: enable

Value	Description
0x0	Timer1 is disabled
0x1	Timer1 is enabled

RW

0x0