TXFTLR 

         Transmit FIFO Threshold Level.
This register controls the threshold value for the transmit FIFO memory.
The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
Module Instance Base Address Register Address
i_spis_1__spis_csr__10da3000__ssi_address_block__SEG_L4_MAIN_spis1_0x0_0x1000 0x10DA3000 0x10DA3018

Size: 32

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_TXFTLR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_TXFTLR

RO 0x0

TFT

RW 0x0

TXFTLR Fields

Bit Name Description Access Reset
31:8 RSVD_TXFTLR 
Reserved bits - Read Only
 RO 0x0
7:0 TFT 
Transmit FIFO Threshold.
Controls the level of entries (or below) at which the transmit FIFO controller
triggers an interrupt. The FIFO depth is configurable in the range 2-256;
this register is sized to the number of address bits needed to access the
FIFO. If you attempt to set this value greater than or equal to the depth
of the FIFO, this field is not written and retains its current value. When
the number of transmit FIFO entries is less than or equal to this value,
the transmit FIFO empty interrupt is triggered.
 RW 0x0