IMR 

         Interrupt Mask Register
Module Instance Base Address Register Address
i_spis_1__spis_csr__10da3000__ssi_address_block__SEG_L4_MAIN_spis1_0x0_0x1000 0x10DA3000 0x10DA302C

Size: 32

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IMR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IMR

RO 0x0

RSVD_MSTIM

RO 0x0

RXFIM

RW 0x1

RXOIM

RW 0x1

RXUIM

RW 0x1

TXOIM

RW 0x1

TXEIM

RW 0x1

IMR Fields

Bit Name Description Access Reset
31:6 RSVD_IMR 
Reserved bits - Read Only
 RO 0x0
5 RSVD_MSTIM 
Reserved field- read-only
 RO 0x0
4 RXFIM 
Receive FIFO Full Interrupt Mask
0 - ssi_rxf_intr interrupt is masked
1 - ssi_rxf_intr interrupt is not masked
Value Description
0x0 RX FIFO Full Interrupt is masked
0x1 RX FIFO Full Interrupt un-masked
RW 0x1
3 RXOIM 
Receive FIFO Overflow Interrupt Mask
0 - ssi_rxo_intr interrupt is masked
1 - ssi_rxo_intr interrupt is not masked
Value Description
0x0 RX FIFO Overflow Interrupt is masked
0x1 RX FIFO Overflow Interrupt un-masked
RW 0x1
2 RXUIM 
Receive FIFO Underflow Interrupt Mask
0 - ssi_rxu_intr interrupt is masked
1 - ssi_rxu_intr interrupt is not masked
Value Description
0x0 RX FIFO Underflow Interrupt is masked
0x1 RX FIFO Underflow Interrupt un-masked
RW 0x1
1 TXOIM 
Transmit FIFO Overflow Interrupt Mask
0 - ssi_txo_intr interrupt is masked
1 - ssi_txo_intr interrupt is not masked
Value Description
0x0 TX FIFO Overflow Interrupt is masked
0x1 TX FIFO Overflow Interrupt un-masked
RW 0x1
0 TXEIM 
Transmit FIFO Empty Interrupt Mask
0 - ssi_txe_intr interrupt is masked
1 - ssi_txe_intr interrupt is not masked
Value Description
0x0 TX FIFO Empty Interrupt is masked
0x1 TX FIFO Empty Interrupt un-masked
RW 0x1