RX_SAMPLE_DLY

         RX Sample Delay.
This register is only valid when the DW_apb_ssi is configured with rxd
sample delay logic (SSI_HAS_RX_SAMPLE_DELAY==1). When the DW_apb_ssi is
not configured with rxd sample delay logic, this register will not exist
and writing to its address location will have no effect; reading from
its address will return zero. This register control the number of ssi_clk
cycles that are delayed (from the default sample time) before the actual
sample of the rxd input occurs. It is impossible to write to this
register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and
disabled by writing to the SSIENR register.


Module Instance	Base Address	Register Address
`i_spim_1__spim_csr__10da5000__ssi_address_block__SEG_L4_MAIN_spim1_0x0_0x1000`	`0x10DA5000`	`0x10DA50F0`

Size: 32

Offset: 0xF0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_RX_SAMPLE_DLY` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_RX_SAMPLE_DLY` `RO 0x0`								`RSD` `RW 0x0`

RX_SAMPLE_DLY Fields

Bit Name Description Access Reset

31:8

Bit	Name	Description	Access	Reset
31:8	`RSVD_RX_SAMPLE_DLY`	Reserved bits - Read Only	`RO`	`0x0`
7:0	`RSD`	Rxd Sample Delay. This register is used to delay the sample of the rxd input port. Each value represents a single ssi_clk delay on the sample of rxd. Note; If this register is programmed with a value that exceeds the depth of the internal shift registers (SSI_RX_DLY_SR_DEPTH) zero delay will be applied to the rxd sample.	`RW`	`0x0`

RSVD_RX_SAMPLE_DLY

Reserved bits - Read Only

RO

0x0

7:0

RSD

Rxd Sample Delay.
This register is used to delay the sample of the rxd input port. Each value
represents a single ssi_clk delay on the sample of rxd. Note; If this register
is programmed with a value that exceeds the depth of the internal shift
registers (SSI_RX_DLY_SR_DEPTH) zero delay will be applied to the rxd sample.

RW

0x0