DR25

         The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for
the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32, then all 32 bits
are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the register is read, data in the
receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write
can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.


Module Instance	Base Address	Register Address
`i_spim_1__spim_csr__10da5000__ssi_address_block__SEG_L4_MAIN_spim1_0x0_0x1000`	`0x10DA5000`	`0x10DA50C4`

Size: 32

Offset: 0xC4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`dr25` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`dr25` `RW 0x0`

DR25 Fields

Bit Name Description Access Reset

31:0

Bit	Name	Description	Access	Reset
31:0	`dr25`	Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0]) of the register are valid. Read = Receive FIFO buffer Write = Transmit FIFO buffer.	`RW`	`0x0`

dr25

Data Register. When writing to this register, you must right-justify the data. Read
data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0]) of the
register are valid.
Read = Receive FIFO buffer
Write = Transmit FIFO buffer.

RW

0x0