DMARDLR

         DMA Receive Data Level.
This register is only valid when DW_apb_ssi is configured with a set of
DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured
for DMA operation, this register will not exist and writing to its address
will have no effect; reading from its address will return zero.


Module Instance	Base Address	Register Address
`i_spim_1__spim_csr__10da5000__ssi_address_block__SEG_L4_MAIN_spim1_0x0_0x1000`	`0x10DA5000`	`0x10DA5054`

Size: 32

Offset: 0x54

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMARDLR` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_DMARDLR` `RO 0x0`								`DMARDL` `RW 0x0`

DMARDLR Fields

Bit Name Description Access Reset

31:8

Bit	Name	Description	Access	Reset
31:8	`RSVD_DMARDLR`	Reserved bits - Read Only	`RO`	`0x0`
7:0	`DMARDL`	Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or above this field value + 1, and RDMAE=1.	`RW`	`0x0`

RSVD_DMARDLR

Reserved bits - Read Only

RO

0x0

7:0

DMARDL

Receive Data Level.
This bit field controls the level at which a DMA request is made by the
receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is
generated when the number of valid data entries in the receive FIFO is
equal to or above this field value + 1, and RDMAE=1.

RW

0x0