RISR

         Raw Interrupt Status Register


Module Instance	Base Address	Register Address
`i_spim_0__spim_csr__10da4000__ssi_address_block__SEG_L4_MAIN_spim0_0x0_0x1000`	`0x10DA4000`	`0x10DA4034`

Size: 32

Offset: 0x34

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_RISR` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_RISR` `RO 0x0`										`MSTIR` `RO 0x0`	`RXFIR` `RO 0x0`	`RXOIR` `RO 0x0`	`RXUIR` `RO 0x0`	`TXOIR` `RO 0x0`	`TXEIR` `RO 0x0`

RISR Fields

Bit Name Description Access Reset

31:6

RSVD_RISR

Reserved bits - Read Only

RO

0x0

MSTIR

Multi-Master Contention Raw Interrupt Status.
This bit field is not present if the DW_apb_ssi is configured as a
serial-slave device.
0 = ssi_mst_intr interrupt is not active prior to masking
1 = ssi_mst_intr interrupt is active prior masking

Value	Description
0x0	Raw Multi-master Contention Interrupt nonactive
0x1	Raw Multi-master Contention Interrupt is active

RO

0x0

RXFIR

Receive FIFO Full Raw Interrupt Status
0 = ssi_rxf_intr interrupt is not active prior to masking
1 = ssi_rxf_intr interrupt is active prior to masking

Value	Description
0x0	Raw RX FIFO Full Interrupt nonactive
0x1	Raw RX FIFO Full Interrupt is active

RO

0x0

RXOIR

Receive FIFO Overflow Raw Interrupt Status
0 = ssi_rxo_intr interrupt is not active prior to masking
1 = ssi_rxo_intr interrupt is active prior masking

Value	Description
0x0	Raw RX FIFO Overflow Interrupt nonactive
0x1	Raw RX FIFO Overflow Interrupt is active

RO

0x0

RXUIR

Receive FIFO Underflow Raw Interrupt Status
0 = ssi_rxu_intr interrupt is not active prior to masking
1 = ssi_rxu_intr interrupt is active prior to masking

Value	Description
0x0	Raw RX FIFO Underflow Interrupt nonactive
0x1	Raw RX FIFO underflow Interrupt is active

RO

0x0

TXOIR

Transmit FIFO Overflow Raw Interrupt Status
0 = ssi_txo_intr interrupt is not active prior to masking
1 = ssi_txo_intr interrupt is active prior masking

Value	Description
0x0	Raw TX FIFO Overflow Interrupt nonactive
0x1	Raw TX FIFO Overflow Interrupt is active

RO

0x0

TXEIR

Transmit FIFO Empty Raw Interrupt Status
0 = ssi_txe_intr interrupt is not active prior to masking
1 = ssi_txe_intr interrupt is active prior masking

Value	Description
0x0	Raw TX FIFO Empty Interrupt nonactive
0x1	Raw TX FIFO Empty Interrupt is active

RO

0x0