ECC_accctrl 

         These bits determine which byte of data/ecc to write to RAM.
Module Instance Base Address Register Address
ecc_sdmmc__ecc_csr__10a20000__ecc_registerBlock__SEG_hps2sdm_be_0x220000_0x10000 0x10A20000 0x10A20078 - 0x10A2016C

Size: 32

Offset: 0x78

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_3

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_3

RO 0x0

RDWR

RW 0x0

Reserved_2

RO 0x0

ECCOVR

RW 0x0

DATAOVR

RW 0x0

ECC_accctrl Fields

Bit Name Description Access Reset
31:9 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
8 RDWR 
Control for read/write.
 RW 0x0
7:2 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
1 ECCOVR 
ECC Data Override.
 RW 0x0
0 DATAOVR 
RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW. 
1’b0: Data override disabled. 
1’b1: Data override enabled.
 RW 0x0