TMOUT

         Timeout Register


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000`	`0x108D1000`	`0x108D1014`

Size: 32

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`DATA_TIMEOUT` `RW 0xFFFFFF`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`DATA_TIMEOUT` `RW 0xFFFFFF`								`RESPONSE_TIMEOUT` `RW 0x40`

TMOUT Fields

Bit Name Description Access Reset

31:8

Bit	Name	Description	Access	Reset
31:8	`DATA_TIMEOUT`	Value for card Data Read Timeout; same value also used for Data Starvation by Host timeout. The timeout counter is started only after the card clock is stopped.Value is in number of card output clocks cclk_out of selected card. Note: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled.	`RW`	`0xFFFFFF`
7:0	`RESPONSE_TIMEOUT`	Response timeout value. Value is in number of card output clocks cclk_out.	`RW`	`0x40`

DATA_TIMEOUT

Value for card Data Read Timeout; same value also used for Data
Starvation by Host timeout. The timeout counter is started only after the card clock is stopped.Value is in number of card output clocks  cclk_out of selected card.
Note: The software timer should be used if the timeout value is in the order
of 100 ms. In this case, read data timeout interrupt needs to be disabled.

RW

0xFFFFFF

7:0

RESPONSE_TIMEOUT

Response timeout value.
Value is in number of card output clocks cclk_out.

RW

0x40