RESP1

         Response Register 1


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000`	`0x108D1000`	`0x108D1034`

Size: 32

Offset: 0x34

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESPONSE1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESPONSE1` `RO 0x0`

RESP1 Fields

Bit Name Description Access Reset

31:0

Bit	Name	Description	Access	Reset
31:0	`RESPONSE1`	Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always “short” for them.	`RO`	`0x0`

RESPONSE1

Register represents bit[63:32] of long response.
When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always “short” for them.

RO

0x0