PWREN
Power Enable Register
| Module Instance | Base Address | Register Address |
|---|---|---|
i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000
|
0x108D1000
|
0x108D1004
|
Size: 32
Offset: 0x4
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
|
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
|
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PWREN Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:1 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
||||||
| 0 |
POWER_ENABLE_0
|
Power on/off switch for up to 16 cards; for example, bit[0] controls card 0.Once power is turned on, firmware should wait for regulator/switch ramp-up time before trying to initialize card.
0-power off
1-power on
Only NUM_CARDS number of bits are implemented.Bit values output to card_power_en port. Optional feature; ports can be used as general-purpose outputs.
|
RW
|
0x0
|