IDSTS 

         
Name: Internal DMAC Status Register
Size: 32 bits
Address Offset: 0x8C
Read/Write access: read/write
Module Instance Base Address Register Address
i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000 0x108D1000 0x108D108C

Size: 32

Offset: 0x8C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_9

RO 0x0

FSM

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FSM

RO 0x0

EB

RO 0x0

AIS

RW 0x0

NIS

RW 0x0

Reserved_5

RO 0x0

CES

RW 0x0

DU

RW 0x0

Reserved_3

RO 0x0

FBE

RW 0x0

RI

RW 0x0

TI

RW 0x0

IDSTS Fields

Bit Name Description Access Reset
31:17 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x0
16:13 FSM 
DMAC FSM present state.
                                                 0  DMA_IDLE
                                                 1  DMA_SUSPEND
                                                 2  DESC_RD
                                                 3  DESC_CHK
                                                 4  DMA_RD_REQ_WAIT
                                                 5  DMA_WR_REQ_WAIT
                                                 6  DMA_RD
                                                 7  DMA_WR
                                                 8  DESC_CLOSE
                                                 This bit is read-only.
 RO 0x0
12:10 EB 
Error Bits. Indicates the type of error that caused a Bus Error. 
Valid only with Fatal Bus
Error bitIDSTS[2] set. This field does not generate an interrupt.
                                                 3’b001  Host Abort received during transmission
                                                 3’b010  Host Abort received during reception
                                                 Others: Reserved
                                                 EB is read-only.
 RO 0x0
9 AIS 
Abnormal Interrupt Summary. Logical OR of the following:
                                                 ■ IDSTS[2]-Fatal Bus Interrupt
                                                 ■ IDSTS[4]-DU bit Interrupt
                                                 Only unmasked bits affect this bit.
This is a sticky bit and must be cleared each time a corresponding bit that causes AIS
to be set is cleared. Writing a 1 clears this bit.
Value Description
0x0 A abnormal interrupt Summary is set
0x1 Writing a 1 clears this bit
RW 0x0
8 NIS 
Normal Interrupt Summary. Logical OR of the following:
                                                 ■ IDSTS[0]-Transmit Interrupt
                                                 ■ IDSTS[1]-Receive Interrupt
Only unmasked bits affect this bit.
This is a sticky bit and must be cleared each time a corresponding bit that causes NIS
to be set is cleared. Writing a 1 clears this bit.
Value Description
0x0 A normal interrupt Summary is set
0x1 Writing a 1 clears this bit
RW 0x0
7:6 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
5 CES 
Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:
                                                 ■ EBE  End Bit Error
                                                 ■ RTO  Response Timeout/Boot Ack Timeout
                                                 ■ RCRC  Response CRC
                                                 ■ SBE  Start Bit Error
                                                 ■ DRTO  Data Read Timeout/BDS timeout
                                                 ■ DCRC  Data CRC for Receive
                                                 ■ RE  Response Error
                                                 Writing a 1 clears this bit.
The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit
is enabled, then the IDMAC aborts on a “response error”; however, it will not abort if the
CES bit is cleared.
Value Description
0x0 Card Error Summary is set
0x1 Writing a 1 clears this bit
RW 0x0
4 DU 
Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit.
Value Description
0x0 Descriptor Unavailable Interrupt is set
0x1 Writing a 1 clears this bit
RW 0x0
3 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
2 FBE 
Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit.
Value Description
0x0 Fatal Bus Error Interrupt is set
0x1 Writing a 1 clears this bit
RW 0x0
1 RI 
Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit.
Value Description
0x0 Receive Interrupt is set
0x1 Writing a 1 clears this bit
RW 0x0
0 TI 
Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a ‘1’ clears this bit.
Value Description
0x0 Transmit Interrupt is set
0x1 Writing a 1 clears this bit
RW 0x0