HCON
Name: Hardware Configuration Register
Size: 32 bits
Address Offset: 0x70
Read/Write access: readHardware Configuration Register
Module Instance | Base Address | Register Address |
---|---|---|
i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000
|
0x108D1000
|
0x108D1070
|
Size: 32
Offset: 0x70
Access: RO
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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HCON Fields
Bit | Name | Description | Access | Reset | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31:28 |
Reserved_13
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
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27 |
ADDR_CONFIG
|
Address configuration
|
RO
|
0x0
|
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26 |
AREA_OPT
|
Area Optimization
|
RO
|
0x0
|
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25:24 |
NUM_CLK_DIC
|
NUM_CLK_DIVIDER - 1 |
RO
|
0x0
|
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23 |
FALSE_PATH
|
Set Clock False Path
|
RO
|
0x1
|
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22 |
HOLD_REG
|
Implement HOLD register
|
RO
|
0x1
|
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21 |
FIFO_RAM_IN
|
FIFO Ram Inside
|
RO
|
0x0
|
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20:18 |
GE_DMA_DATA_WIDTH
|
Generic DMA Data Width 000 - 16 bits 001 - 32 bits 010 - 64 bits others - reserved |
RO
|
0x1
|
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17:16 |
DMA_IF
|
DMA Interface
|
RO
|
0x0
|
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15:10 |
H_ADDR_WIDTH
|
H Address Width 00 to 7 reserved 8 9 bits 9 10 bits … 31 32 bits 32 to 63 reserved |
RO
|
0xC
|
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9:7 |
H_DATA_WIDTH
|
H Data Width 000 - 16 bits 001 - 32 bits 010 - 64 bits others - reserved |
RO
|
0x1
|
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6 |
BUS_TYPE
|
Bus type
|
RO
|
0x0
|
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5:1 |
NUM_CARD
|
NUM_CARD - 1 |
RO
|
0x0
|
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0 |
CARD_TYPE
|
Card type
|
RO
|
0x1
|