ENABLE_SHIFT

         
Name: Enable Phase Shift Register
Address Offset: 0x110
Read/Write access: read/write


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000`	`0x108D1000`	`0x108D1110`

Size: 32

Offset: 0x110

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`														`ENABLE_SHIFT_CARD0` `RW 0x0`

ENABLE_SHIFT Fields

Bit Name Description Access Reset

31:2

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

1:0

ENABLE_SHIFT_CARD0

Control for the amount of phase shift provided on the default 
enables in the design. Two bits are assigned for each card/slot. For example, bits[1:0] control slot0 and indicate the following.
                                                 ■ 00  Default phase shift
                                                 ■ 01  Enables shifted to next immediate positive edge
                                                 ■ 10  Enables shifted to next immediate negative edge
                                                 ■ 11  Reserved

Value	Description
0x0	Default phase shift
0x1	Enables shifted to next immediate positive edge
0x2	Enables shifted to next immediate negative edge
0x3	Reserved

RW

0x0