DEBNCE

         
Name: Debounce Count Register
Size: 32 bits
Address Offset: 0x64
Read/write access: write/read


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000`	`0x108D1000`	`0x108D1064`

Size: 32

Offset: 0x64

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`								`DEBOUNCE_COUNT` `RW 0xFFFFFF`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`DEBOUNCE_COUNT` `RW 0xFFFFFF`

DEBNCE Fields


Bit	Name	Description	Access	Reset
31:24	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
23:0	`DEBOUNCE_COUNT`	Number of host clocks (clk) used by debounce filter logic; typical debounce time is 5-25 ms.	`RW`	`0xFFFFFF`