CLKENA

         Clock Enable Register


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000`	`0x108D1000`	`0x108D1010`

Size: 32

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_2` `RO 0x0`															`CCLK_LOW_POWER_0` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`															`CCLK_ENABLE_0` `RW 0x0`

CLKENA Fields

Bit Name Description Access Reset

31:17

Reserved_2

Reserved bitfield added by Magillem

RO

0x0

CCLK_LOW_POWER_0

Low-power control for up to 16 SD card clocks and one MMC card clock supported.
                                                 0-Non-low-power mode
                                                 1-Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped).
In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_low_power[0] is used.

Value	Description
0x0	Non Low Power mode
0x1	Low Power mode

RW

0x0

15:1

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

CCLK_ENABLE_0

Clock-enable control for up to 16 SD card clocks and one MMC card clock supported.
                                                 0-Clock disabled
                                                 1-Clock enabled
In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used.

Value	Description
0x0	Clock disabled
0x1	Clock enabled

RW

0x0