CARDTHRCTL 

         
Name: Card Threshold Control Register
Size: 32 bits
Address Offset: 0x100
Read/Write access: read/write
Module Instance Base Address Register Address
i_sdmmc__sdmmc_csr__108d1000__sdmmc_block__SEG_hps2sdm_be_0x1000_0x1000 0x108D1000 0x108D1100

Size: 32

Offset: 0x100

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

RO 0x0

CARDRDTHRESHOLD

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_3

RO 0x0

CARDWRTHREN

RO 0x0

BUSY_CLR_INT_EN

RW 0x0

CARDRDTHREN

RW 0x0

CARDTHRCTL Fields

Bit Name Description Access Reset
31:29 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
28:16 CARDRDTHRESHOLD 
Card Read Threshold size; N depends on the FIFO size:
                                                 ■ N = 27  FIFO_DEPTH is 128
                                                 ■ N = 26  FIFO_DEPTH is 64
                                                 ■ N = 25  FIFO_DEPTH is 32
                                                 ■ N = 24  FIFO_DEPTH is 16
                                                 ■ N = 23  FIFO_DEPTH is 8
Note: The maximum programmable value of Card Read Threshold size is 512.
 RW 0x0
15:3 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
2 CARDWRTHREN 
Card Write Threshold Enable
                                                 ■ 1'b0 - Card Write Threshold disabled
                                                 ■ 1'b1 - Card Write Threshold enabled. Host Controller initiates 
                                                   Write Transfer only if CardThreshold amount of data is 
                                                   available in transmit FIFO.
Value Description
0x0 Card Write Threshold disabled
0x1 Card Write Threshold enabled
RO 0x0
1 BUSY_CLR_INT_EN 
Busy Clear Interrupt generation:
                                                 ■ 1'b0 - Busy Clear Interrupt disabled
                                                 ■ 1'b1 - Busy Clear Interrupt enabled
Note: The application can disable this feature if it does not want to wait for a Busy Clear Interrupt. For example, in a multi-card scenario, the application can switch to the other card without waiting for a busy to be completed. In such cases, the application can use the polling method to determine the status of busy. By default this feature is disabled and backward-compatible to the legacy drivers where polling is used.
Value Description
0x0 Busy Clear Interrupt disabled
0x1 Busy Clear Interrupt enabled
RW 0x0
0 CARDRDTHREN 
Card Read Threshold Enable
                                                 ■ 1'b0 - Card Read Threshold disabled
                                                 ■ 1'b1 - Card Read Threshold enabled. Host Controller initiates 
                                                   Read Transfer only if CardRdThreshold amount of space is 
                                                   available in receive FIFO.
Value Description
0x0 Card Read Threshold disabled
0x1 Card Read Threshold enabled
RW 0x0