GICR3_ICFGR1

         GICR3_ICFGR1


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRsgi3`	`0x1D0D0000`	`0x1D0D0C04`

Size: 32

Offset: 0xC04

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`int_config15` `RW 0x0`		`int_config14` `RW 0x0`		`int_config13` `RW 0x0`		`int_config12` `RW 0x0`		`int_config11` `RW 0x0`		`int_config10` `RW 0x0`		`int_config9` `RW 0x0`		`int_config8` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`int_config7` `RW 0x0`		`int_config6` `RW 0x0`		`int_config5` `RW 0x0`		`int_config4` `RW 0x0`		`int_config3` `RW 0x0`		`int_config2` `RW 0x0`		`int_config1` `RW 0x0`		`int_config0` `RW 0x0`

GICR3_ICFGR1 Fields


Bit	Name	Description	Access	Reset
31:30	`int_config15`	int_config15	`RW`	`0x0`
29:28	`int_config14`	int_config14	`RW`	`0x0`
27:26	`int_config13`	int_config13	`RW`	`0x0`
25:24	`int_config12`	int_config12	`RW`	`0x0`
23:22	`int_config11`	int_config11	`RW`	`0x0`
21:20	`int_config10`	int_config10	`RW`	`0x0`
19:18	`int_config9`	int_config9	`RW`	`0x0`
17:16	`int_config8`	int_config8	`RW`	`0x0`
15:14	`int_config7`	int_config7	`RW`	`0x0`
13:12	`int_config6`	int_config6	`RW`	`0x0`
11:10	`int_config5`	int_config5	`RW`	`0x0`
9:8	`int_config4`	int_config4	`RW`	`0x0`
7:6	`int_config3`	int_config3	`RW`	`0x0`
5:4	`int_config2`	int_config2	`RW`	`0x0`
3:2	`int_config1`	int_config1	`RW`	`0x0`
1:0	`int_config0`	int_config0	`RW`	`0x0`