GICR3_CFGID1

         GICR3_CFGID1


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRsgi3`	`0x1D0D0000`	`0x1D0DF004`

Size: 32

Offset: 0xF004

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Version` `RO 0xA`				`REVAND` `RO 0x0`				`RESERVED1` `RO 0x0`				`PPIsPerProcessor` `RO 0xF`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED0` `RO 0x0`			`DirectUpstream` `RO 0x1`	`NumCPUs` `RO 0x4`								`NumARE0CPUs` `RO 0x0`

GICR3_CFGID1 Fields


Bit	Name	Description	Access	Reset
31:28	`Version`	Version	`RO`	`0xA`
27:24	`REVAND`	REVAND	`RO`	`0x0`
23:20	`RESERVED1`	RESERVED1	`RO`	`0x0`
19:16	`PPIsPerProcessor`	PPIsPerProcessor	`RO`	`0xF`
15:13	`RESERVED0`	RESERVED0	`RO`	`0x0`
12	`DirectUpstream`	DirectUpstream	`RO`	`0x1`
11:4	`NumCPUs`	NumCPUs	`RO`	`0x4`
3:0	`NumARE0CPUs`	NumARE0CPUs	`RO`	`0x0`