GICR2_CFGID0

         GICR2_CFGID0


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRsgi2`	`0x1D0B0000`	`0x1D0BF000`

Size: 32

Offset: 0xF000

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Af3width` `RO 0x0`				`Af2width` `RO 0x0`				`Af1width` `RO 0x2`				`Af0width` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`TargetlistWidth` `RO 0x0`				`ECCSupport` `RO 0x1`	`RESERVED0` `RO 0x0`		`PPINumber` `RO 0x0`

GICR2_CFGID0 Fields


Bit	Name	Description	Access	Reset
31:28	`Af3width`	Af3width	`RO`	`0x0`
27:24	`Af2width`	Af2width	`RO`	`0x0`
23:20	`Af1width`	Af1width	`RO`	`0x2`
19:16	`Af0width`	Af0width	`RO`	`0x0`
15:12	`TargetlistWidth`	TargetlistWidth	`RO`	`0x0`
11	`ECCSupport`	ECCSupport	`RO`	`0x1`
10:9	`RESERVED0`	RESERVED0	`RO`	`0x0`
8:0	`PPINumber`	PPINumber	`RO`	`0x0`